Mitigating the SERs of large combinational circuits by using half guard band technique in CMOS bulk technology.
Bin LiangYankang DuHui XuPublished in: IEICE Electron. Express (2014)
Keyphrases
- cmos technology
- high speed
- delay insensitive
- analog vlsi
- asynchronous circuits
- low power
- circuit design
- cost effective
- vlsi circuits
- rapid development
- power consumption
- logic circuits
- low voltage
- random access memory
- power dissipation
- case study
- chip design
- high level synthesis
- low cost
- technological advances
- key technologies
- learning environment
- floating gate
- neural network
- nm technology