Automated verification of temporal properties specified as state machines in VHDL.
Yatin Vasant HoskoteJacob A. AbrahamDonald S. FussellPublished in: Great Lakes Symposium on VLSI (1995)
Keyphrases
- automated verification
- temporal properties
- model checking
- state machines
- reactive systems
- state machine
- finite state machines
- temporal logic
- formal verification
- petri net
- formal specification
- formal methods
- recurrent networks
- sequence diagrams
- machine learning
- fault tolerant
- fuzzy logic
- artificial intelligence
- genetic algorithm
- automated reasoning
- embedded systems
- social networks