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Tiered-latency DRAM: A low latency and low cost DRAM architecture.
Donghyuk Lee
Yoongu Kim
Vivek Seshadri
Jamie Liu
Lavanya Subramanian
Onur Mutlu
Published in:
HPCA (2013)
Keyphrases
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low latency
low cost
highly efficient
real time
main memory
high density
high speed
high bandwidth
embedded dram
memory subsystem
high throughput
low voltage
low power
stream processing
virtual machine
cost effective
data structure
cmos technology
massive scale
data sets
continuous query processing
low complexity