VHDL synthesis of a 0.7 μ CMOS ASIC for block segmentation of digital images.

J. Huylebroeck D. Martiny Piet Boekaerts Jan Cornelis

Published in: ICECS (1996)

Keyphrases

digital images
circuit design
integrated circuit
hardware implementation
image segmentation
image blocks
segmentation algorithm
single chip
level set
fully automatic
shape prior
segmentation method
region growing
medical images
digital camera
object segmentation
high speed
low cost
multiscale
edge detection