An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.
Shouyi YinPeng OuyangJianxun YangTianyi LuXiudong LiLeibo LiuShaojun WeiPublished in: VLSI Circuits (2018)
Keyphrases
- energy efficient
- ultra high
- neural network
- multi core architecture
- high speed
- low cost
- wireless sensor networks
- cmos technology
- energy consumption
- energy efficiency
- sensor networks
- power consumption
- parallel processing
- low power
- data handling
- high resolution
- base station
- random access memory
- data dissemination
- metal oxide semiconductor
- hardware implementation
- silicon on insulator
- routing protocol
- data transmission
- image sensor
- routing algorithm
- multi core processors
- instruction set
- computer architecture
- field programmable gate array
- associative memory
- sensor nodes
- data processing
- ibm power processor
- query processing
- database systems
- image processing