Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs.
Pietro BuccellaCamillo StefanucciHao ZouYasser MoursyRamy IskanderJean-Michel SalleseMaher KayalPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)