A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors.
Xiantuo RaoTeng WangXin'an WangYinhui WangPublished in: ASICON (2013)
Keyphrases
- low power
- high efficiency
- single chip
- high speed
- embedded processors
- low cost
- low power consumption
- power consumption
- vlsi architecture
- logic circuits
- digital signal processing
- cmos technology
- embedded systems
- ultra low power
- high accuracy
- power dissipation
- high power
- design methodology
- mixed signal
- nm technology
- gate array
- dynamic random access memory
- design process
- circuit design
- wireless transmission
- main memory