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Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM.
Tomohiro Korikawa
Akio Kawabata
Fujun He
Eiji Oki
Published in:
IEEE Access (2020)
Keyphrases
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main memory
real time
memory subsystem
distributed processing
dynamic random access memory
query processing
network architecture
parallel architecture
memory hierarchy
data structure
high speed
processing units
memory management
packet switching
gigabit ethernet
instruction set