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An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.

Daeyeon KimVikas ChandraRobert C. AitkenDavid T. BlaauwDennis Sylvester
Published in: ISLPED (2012)
Keyphrases
  • pulse width
  • management system
  • bit parallel
  • real time
  • co occurrence
  • software architecture
  • high voltage
  • information extraction
  • power system
  • line segments
  • line drawings
  • design considerations