CAESAR: Coherence-Aided Elective and Seamless Alternative Routing via on-chip FPGA.
Shahin RoozkhoshDenis HoornaertRenato MancusoPublished in: RTSS (2022)
Keyphrases
- network topologies
- network topology
- high speed
- single chip
- low cost
- programmable logic
- low power
- analog vlsi
- low power consumption
- vlsi implementation
- real time
- systolic array
- hardware implementation
- network on chip
- parallel hardware
- hardware design
- field programmable gate array
- context awareness
- high density
- end to end
- data acquisition