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Guarded evaluation: pushing power management to logic synthesis/design.

Vivek TiwariSharad MalikPranav Ashar
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
  • logic synthesis
  • power management
  • power consumption
  • response time
  • real time
  • machine learning
  • high speed
  • design process
  • embedded systems