Formal verification of pipelined processors with load-value prediction.
Miroslav N. VelevPublished in: HLDVT (2004)
Keyphrases
- formal verification
- model checking
- prediction accuracy
- automated verification
- prediction algorithm
- model checker
- symbolic model checking
- bounded model checking
- load forecasting
- load balancing
- prediction error
- program slicing
- temporal logic
- parallel algorithm
- parallel computing
- parallel architecture
- functional verification
- shared memory
- load balance
- fuzzy sets
- data flow
- prediction model
- parallel processing
- short term
- distributed systems