A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Kyunghoon KimJoo-Hyung ChaeJaehyeok YangJihyo KangGang-Sik LeeSang-Yeon ByeonYoungtaek KimBoram KimDong-Hyun KimYeongmuk ChoKangmoo ChoiHyeongyeol ParkJunghwan JiSera JeongYongsuk JooJaehoon ChaMinsoo ParkHongdeuk KimSijun ParkKyubong KongSunho KimSangkwon LeeJunhyun ChunHyungsoo KimSeon-Yong ChaPublished in: ISSCC (2021)