Verifying parallel dataflow transformations with model checking and its application to FPGAs.
Robert J. StewartBernard BerthomieuPaulo GarciaIdris IbrahimGreg MichaelsonAndrew M. WallacePublished in: J. Syst. Archit. (2019)
Keyphrases
- model checking
- temporal logic
- parallel computing
- formal verification
- automated verification
- temporal properties
- model checker
- field programmable gate array
- formal specification
- finite state machines
- finite state
- timed automata
- shared memory
- verification method
- formal methods
- epistemic logic
- reachability analysis
- symbolic model checking
- bounded model checking
- computation tree logic
- partial order reduction
- concurrent systems
- pspace complete
- massively parallel
- process algebra
- reactive systems
- transition systems
- linear temporal logic
- modal logic
- asynchronous circuits
- control flow
- abstract interpretation
- alternating time temporal logic