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Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuits.

Mohammad FawazNader KobrosliAhmad ChkeirAli ChehabAyman I. Kayssi
Published in: ICECS (2010)
Keyphrases
  • high speed
  • data analysis
  • steady state
  • delay insensitive
  • analog vlsi
  • data sets
  • real world
  • statistical analysis
  • future development
  • digital circuits
  • power dissipation