A shift-register-based QCA memory architecture.
Baris TaskinAndy ChiuJonathan SalkindDaniel VenutoloPublished in: NANOARCH (2007)
Keyphrases
- shift register
- hardware implementation
- high speed
- cellular automata
- management system
- memory management
- random number generator
- memory requirements
- real time
- processing units
- software architecture
- associative memory
- computer vision
- real world
- memory access
- level parallelism
- memory subsystem
- memory hierarchy
- processing elements
- main memory
- software development
- low cost
- neural network