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Modular verification of timed circuits using automatic abstraction.
Hao Zheng
Eric Mercer
Chris J. Myers
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2003)
Keyphrases
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asynchronous circuits
petri net
model checking
bounded model checking
high speed
artificial intelligence
data sets
databases
data driven
fully automatic
formal verification
analog circuits
verification method
modular structure
delay insensitive