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A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.

Woo-Rham BaeGyu-Seob JeongKwanseo ParkSung-Yong ChoYoonsoo KimDeog-Kyoon Jeong
Published in: ESSCIRC (2014)
Keyphrases
  • protection scheme
  • high speed
  • power consumption
  • bit vector
  • bit string
  • pseudorandom
  • logical operations
  • data sets
  • random access memory
  • magnetic tape
  • bit parallel