A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks.
Heshan ZhangZhenyu LiuGuanwen ZhangJiwu DaiXiaocong LianWei ZhouXiangyang JiPublished in: GlobalSIP (2019)
Keyphrases
- convolutional neural networks
- field programmable gate array
- floating point arithmetic
- floating point
- convolutional network
- hardware implementation
- embedded systems
- image processing algorithms
- low cost
- parallel computing
- real time
- signal processing
- instruction set
- parallel implementation
- computing systems
- database systems
- image processing
- artificial intelligence