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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Chang-Kyo LeeYoon-Joo EomJin-Hee ParkJunha LeeHye-Ran KimKihan KimYoung ChoiHo-Jun ChangJonghyuk KimJong-Min BangSeungjun ShinHanna ParkSu-Jin ParkYoung-Ryeol ChoiHoon LeeKyong-Ho JeonJae-Young LeeHyo-Joo AhnKyoung-Ho KimJung-Sik KimSoobong ChangHyong-Ryol HwangDuyeul KimYoon-Hwan YoonSeok-Hun HyunJoon-Young ParkYoon-Gyu SongYoun-Sik ParkHyuck-Joon KwonSeung-Jun BaeTae-Young OhIndal SongYong-Cheol BaeJung-Hwan ChoiKwang-Il ParkSeong-Jin JangGyo-Young Jin
Published in: ISSCC (2017)
Keyphrases
  • high speed
  • camera calibration
  • management system
  • power consumption
  • real time
  • vlsi implementation
  • neural network
  • learning scheme
  • data sets
  • learning algorithm
  • knowledge base
  • classification scheme
  • search mechanism