A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture.
Yusuke OikeMakoto IkedaKunihiro AsadaPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- high speed
- distance estimation
- low voltage
- multi processor
- low power
- cmos technology
- parallel processing
- parallel architecture
- design considerations
- instruction set
- real time
- level parallelism
- multi core processors
- processing elements
- computer architecture
- associative memory
- distributed memory
- multithreading
- gigabit ethernet
- random access memory
- data sets
- shared memory
- parallel computing
- frame rate
- intelligent tutoring systems
- single instruction multiple data