Semidigital PLL Design for Low-Cost Low-Power Clock Generation.
Ni XuWoogeun RheeZhihua WangPublished in: J. Electr. Comput. Eng. (2011)
Keyphrases
- low power
- low cost
- single chip
- power consumption
- low power consumption
- high speed
- vlsi architecture
- logic circuits
- digital signal processing
- cmos technology
- high power
- gate array
- mixed signal
- power dissipation
- vlsi circuits
- real time
- ultra low power
- wireless transmission
- hardware and software
- embedded systems
- digital camera
- image sensor
- power reduction
- signal processor
- image processing
- power saving
- energy saving
- high density
- energy dissipation
- nm technology