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Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing.
Shlomo Greenberg
Ido Bloch
Moti Horwitz
Avishay Maman
Published in:
ICECS (2004)
Keyphrases
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high speed
optimization algorithm
low cost
higher level
tree structure
binary tree
optimization problems
power consumption
power losses
analog vlsi
optimization process
global optimization
genetic algorithm
optimization method
index structure
levels of abstraction
evolutionary algorithm
neural network