Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST.
Diego GarciaJavier GranizoLuis HernándezPublished in: AICAS (2023)
Keyphrases
- circuit design
- high speed
- analog vlsi
- flip flops
- delay insensitive
- cmos technology
- nearest neighbor
- vlsi circuits
- neural network
- low voltage
- low cost
- frequency domain
- low power
- analog circuits
- stochastic resonance
- probabilistic inference
- digital circuits
- inference process
- handwritten digits
- training algorithm
- handwritten digit recognition
- bayesian networks
- neuron model
- real time
- nm technology
- asynchronous circuits
- focal plane
- hand written
- power dissipation
- power consumption