Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms.
Kunwar SinghAman JainAviral MittalVinay YadavAtul Anshuman SinghAnmoll Kumar JainManeesha GuptaPublished in: Integr. (2018)
Keyphrases
- low power
- logic circuits
- evolutionary algorithm
- high speed
- power dissipation
- power consumption
- low cost
- multi objective
- optimization problems
- gate array
- differential evolution
- image sensor
- digital signal processing
- multi objective optimization
- tunnel diode
- functional decomposition
- circuit design
- differential evolution algorithm
- cmos technology
- logic synthesis
- real time
- dynamic programming
- genetic algorithm