A 4-Kb low power 4-T SRAM design with negative word-line gate drive.
Chua-Chin WangChing-Li LeeWun-Ji LinPublished in: ISCAS (2006)
Keyphrases
- low power
- cmos technology
- power consumption
- single chip
- low cost
- low power consumption
- vlsi architecture
- nm technology
- logic circuits
- high speed
- power reduction
- digital signal processing
- power dissipation
- gate array
- high power
- mixed signal
- knowledge base
- vlsi circuits
- low voltage
- power management
- wireless transmission
- power saving
- signal processing
- parallel processing
- design process