Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only).
Yu BaiAbigail Fuentes-RiveraMingjie LinMike RieraPublished in: FPGA (2013)
Keyphrases
- processing elements
- computational power
- memory management
- multithreading
- low level
- associative memory
- hardware implementation
- hardware architecture
- level parallelism
- higher level
- parallel processing
- computer vision
- parallel execution
- memory access
- dynamic graph
- memory bandwidth
- parallel architectures
- parallel computers
- parallel computing