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The timing control design of 65nm block RAM in FPGA.
Xinrui Zhang
Jian Wang
Dan Chen
Jinmei Lai
Lichun Bao
Xueling Liu
Published in:
ASICON (2013)
Keyphrases
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data acquisition
low cost
case study
signal processing
design process
real time
control strategy
design principles
control method
design considerations
real time control
data structure
high speed
image quality
controller design
mechanical systems
verilog hdl