Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits.
Michael FigueiredoTomasz MichalakJoão GoesLuís GomesPawel SniatalaPublished in: ICECS (2009)
Keyphrases
- delay insensitive
- high speed
- power consumption
- floating gate
- chip design
- asynchronous circuits
- random access memory
- low power
- logic synthesis
- logic circuits
- vlsi circuits
- analog vlsi
- circuit design
- digital circuits
- focal plane
- cmos technology
- design considerations
- low voltage
- power dissipation
- modal logic
- logic programming
- high quality
- pseudorandom
- improved algorithm
- logic programs
- flip flops
- shift register