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A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector.
Dae Hyun Kwon
Minkyu Kim
Sung-Geun Kim
Woo-Young Choi
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
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