Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions.
K. PraghashS. Arun MethaB. Sai TanujaK. PreethiN. P. N. S. ChandanaPublished in: Wirel. Pers. Commun. (2022)
Keyphrases
- low power
- power dissipation
- logic circuits
- cmos technology
- power consumption
- vlsi architecture
- single chip
- high speed
- low cost
- ultra low power
- gate array
- digital signal processing
- low power consumption
- vlsi circuits
- design process
- high power
- mixed signal
- design methodology
- power reduction
- circuit design
- efficient implementation
- image sensor
- low voltage
- delay insensitive
- signal processor
- nm technology
- hardware and software