Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback
Peter-Michael SeidelPublished in: ACL2 (2011)
Keyphrases
- floating point
- low power
- formal verification
- high speed
- power consumption
- low cost
- model checking
- fixed point
- single chip
- floating point arithmetic
- low power consumption
- instruction set
- image sensor
- digital signal processing
- vlsi architecture
- logic circuits
- gate array
- sparse matrices
- mixed signal
- power reduction
- real time
- finite state machines
- parallel algorithm