Exact Synthesis of Reversible Logic Circuits using Model Checking.
Rajarshi RayArup DekaKamalika DattaPublished in: CoRR (2017)
Keyphrases
- model checking
- logic circuits
- functional decomposition
- logic synthesis
- temporal logic
- low power
- finite state machines
- formal specification
- finite state
- temporal properties
- model checker
- automated verification
- formal verification
- tunnel diode
- computation tree logic
- timed automata
- verification method
- symbolic model checking
- reachability analysis
- bounded model checking
- markov chain
- pspace complete
- epistemic logic
- low cost
- formal methods
- boolean functions
- transition systems
- linear temporal logic
- search algorithm
- deterministic finite automaton
- concurrent systems
- asynchronous circuits