An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing.
Kyeong-Ryeol BaeSeung-Ho OkHyeon-Sik SonSang Yoon OhYong-Hwan LeeByungin MoonPublished in: FGIT-FGCN (1) (2011)
Keyphrases
- packet switching
- parallel architecture
- abstraction layer
- content addressable memory
- processing elements
- gigabit ethernet
- network layer
- high speed
- real time
- network architecture
- protocol stack
- application layer
- hierarchical architecture
- data flow
- memory management
- distributed processing
- middle layer
- network design
- distributed computing environment
- parallel processing
- multi layer
- cross layer
- computation intensive
- internet traffic
- transmission rate
- switched networks
- functional units
- differentiated services
- destination node
- network resources
- central processor
- communication networks
- network traffic
- peer to peer
- wireless sensor networks
- computer networks
- level parallelism
- hardware implementation
- parallel processors
- distributed memory