FPGA-based architecture for hardware compression/decompression of wide format images.
Mohamed AkilLaurent PerrotonThierry GrandpierrePublished in: J. Real Time Image Process. (2006)
Keyphrases
- hardware architecture
- image compression
- image database
- input image
- hardware design
- test images
- image data
- data compression
- image analysis
- hardware implementation
- compression algorithm
- image features
- compression scheme
- original images
- three dimensional
- ground truth
- image classification
- compression ratio
- edge detection
- real time
- hardware architectures
- image registration
- high compression ratio
- region of interest
- software implementation
- low cost
- image processing algorithms
- object recognition
- lossy compression
- image regions
- field programmable gate array
- hardware and software
- pattern matching
- image retrieval
- metadata