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2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology.

Masakazu KurisuMakoto KanekoTetsuyuki SuzakiAkira TanabeMitsuhiro TogoAkio FurukawaTakao TamuraKen NakajimaKazuyoshi Yoshida
Published in: IEEE J. Solid State Circuits (1996)
Keyphrases
  • power consumption
  • cmos technology
  • low power
  • spl times
  • power management
  • high speed
  • power dissipation
  • error correcting codes
  • low voltage
  • low cost
  • real time
  • pattern recognition
  • regular expressions