LAPP: A Low Power Array Accelerator with Binary Compatibility.
Naveen DevisettiTakuya IwakamiKazuhiro YoshimuraTakashi NakadaJun YaoYasuhiko NakashimaPublished in: IPDPS Workshops (2011)
Keyphrases
- low power
- low cost
- power consumption
- high speed
- image sensor
- single chip
- vlsi circuits
- low power consumption
- high power
- digital signal processing
- wireless transmission
- logic circuits
- focal plane
- mixed signal
- vlsi architecture
- cmos technology
- non binary
- general purpose
- delay insensitive
- parallel implementation
- gate array