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Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.
Masoumeh Ebrahimi
Masoud Daneshtalab
Pasi Liljeberg
Juha Plosila
Hannu Tenhunen
Published in:
J. Comput. Syst. Sci. (2013)
Keyphrases
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high speed
inter layer
multithreading
base layer
artificial neural networks
hardware implementation
neural network
bit rate
rate distortion
bitstream
multi layer
scalable video coding