Speeding Up AES By Extending a 32 bit Processor Instruction Set.

Guido Bertoni Luca Breveglieri Roberto Farina Francesco Regazzoni

Published in: ASAP (2006)

Keyphrases

instruction set
instruction set architecture
advanced encryption standard
floating point
s box
block cipher
computer architecture
application specific
embedded systems
level parallelism
memory subsystem
ibm power processor
databases
parallel processing
software systems
low cost
information systems