Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two.

Stephan Held Sophie Theresa Spirkl

Published in: CoRR (2015)

Keyphrases

logic circuits
depth map
shift register
high speed
depth information
linear model
data flow
power dissipation
real time
multi class
low cost
memory requirements
space complexity
multi valued
digital circuits