CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC.
Maher AssaadDavid R. S. CummingPublished in: SoC (2007)
Keyphrases
- high speed
- circuit design
- low power
- single chip
- low cost
- cmos image sensor
- cmos technology
- design process
- chip design
- power dissipation
- low power consumption
- design methodology
- analog vlsi
- power consumption
- embedded systems
- nm technology
- ultra low power
- analog to digital converter
- functional verification
- vlsi implementation
- case study
- dynamic range
- data acquisition
- communication networks