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A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers.
Jubee Tada
Ryusuke Egawa
Kazushige Kawai
Hiroaki Kobayashi
Gensuke Goto
Published in:
3DIC (2011)
Keyphrases
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floating point
fixed point
square root
instruction set
high speed
sparse matrices
interval arithmetic
floating point arithmetic
multi view
fine grained
power consumption