High-speed interfaces for analog, iterative VLSI decoders.
Markus HelfensteinFelix LustenbergerA. LoeligerFelix TarköyGeorge S. MoschytzPublished in: ISCAS (2) (1999)
Keyphrases
- high speed
- low power
- focal plane
- vlsi architecture
- mixed signal
- signal processing
- real time
- vlsi circuits
- gigabit ethernet
- processor array
- analog vlsi
- data driven
- frame rate
- circuit design
- power reduction
- iterative optimization
- single chip
- neural network
- databases
- decoding algorithm
- high speed networks
- infrared
- human computer interaction
- image quality
- user interface
- image sequences