A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology.

Se-Chun Park Seung-Baek Park Soo-Won Kim

Published in: ICCE (2015)

Keyphrases

fully integrated
leakage current
low voltage
cmos technology
phase locked loop
low power
power line
parallel processing
power consumption
workflow management
high voltage
multipath
power dissipation
design considerations
low cost
power management
information systems
high speed
database systems
e learning