Accelerating Binary-Matrix Multiplication on FPGA.

Debjyoti Bhattacharjee Anupam Chattopadhyay Ricardo Jack Liwongan

Published in: SoCC (2019)

Keyphrases

matrix multiplication
message passing
hardware implementation
high speed
low cost
matrix factorization
distributed memory
real time image processing
field programmable gate array
real time
hardware architecture
object recognition
preprocessing
signal processing