A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations.
K. SridharanT. K. PriyaPublished in: IEEE Trans. Ind. Electron. (2007)
Keyphrases
- field programmable gate array
- graph construction
- hardware implementation
- hardware architecture
- fpga device
- image processing
- knn
- embedded systems
- graph based semi supervised learning
- training set
- machine learning
- active learning
- dimensionality reduction
- k nearest neighbor
- semi supervised learning
- parallel computing