Reconfigurable decoder architectures for Raptor codes.
Hady ZeineddineMohammad M. MansourPublished in: ICASSP (2011)
Keyphrases
- error control
- reed solomon
- decoding algorithm
- low density parity check
- error correction
- joint source channel
- ldpc codes
- reconfigurable architecture
- low cost
- low complexity
- turbo codes
- heterogeneous computing
- interconnection networks
- functional units
- convolutional codes
- error detection
- error concealment
- general purpose
- channel coding
- distributed video coding
- decoding process
- systolic array
- hardware implementation
- coding scheme