The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation.
Oscar PérezYves BervillerCamel TanougastSerge WeberPublished in: J. Univers. Comput. Sci. (2007)
Keyphrases
- hardware implementation
- detection algorithm
- times faster
- computational cost
- high accuracy
- preprocessing
- cost function
- dynamic programming
- matching algorithm
- worst case
- learning algorithm
- fpga implementation
- software implementation
- hardware architecture
- optimization algorithm
- probabilistic model
- significant improvement
- computational complexity
- optimal solution
- real time
- low cost
- parallel implementation
- image processing algorithms
- objective function
- advanced encryption standard