A lean FPGA soft processor built using a DSP block.
Hui Yan CheahSuhaib A. FahmyDouglas L. MaskellChidamber KulkarniPublished in: FPGA (2012)
Keyphrases
- systolic array
- digital signal
- high speed
- verilog hdl
- signal processing
- parallel architecture
- real time image processing
- digital signal processing
- single chip
- gate array
- data flow
- low power
- field programmable gate array
- hardware implementation
- parallel processing
- fpga device
- video processing
- power consumption
- low cost
- image processing
- hardware architecture
- low power consumption
- digital signal processor