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A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS.
Jun-Hwan Jang
Hui-Dong Gwon
Tae-Hwang Kong
Jun-Hyeok Yang
Byong-Deok Choi
Published in:
IEEE J. Solid State Circuits (2022)
Keyphrases
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power supply
data conversion
successive approximation
electrical power
high frequency
analog vlsi
intelligent control
single phase
power quality
circuit design
rbf neural network
cmos technology
control unit
energy dissipation
neural network
focal plane
low voltage